AUTHORS: Meenakshi Agarwal, Tarun Kumar Rawat

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ABSTRACT: The second-order all-pass section is the main building block of the lattice wave digital filters (WDFs). The all-pass sections are conventionally realized using two port adaptors. In this paper, second-order all-pass sections are replaced with three port parallel adaptors. These adaptors, implemented with canonic signed digit coefficients, are proposed to increase maximal sampling frequency of lattice WDFs. The proposed implementation of three port parallel adaptors reduces the latency of the critical loop by reducing the components (adders and multipliers). Further increase in maximal sampling frequency is obtained by integrating these three port parallel adaptors using carry propagation adders (CPA) designed with low power and high performance 1-bit full adders, registers as delay elements and binary multipliers. Here, multipliers are implemented using a network of shifts and adders (or subtractors). An example of a filter implementation where the proposed approaches are applied, is presented. In this example multiple-constant multiplication technique is applied to reduce the number of adders in the implementation of multipliers. The sections are integrated using Design Architect and simulated using Eldonet tools of Mentor Graphics V2008 and tested by applying number of input vectors. The results are compared with the conventional second-order all-pass sections. The comparison shows the increase in maximal sampling frequency by approximately 46% at the cost of about 13% increase in area.

KEYWORDS: VLSI design, wave digital filters, three port adaptor, full adder, delays

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